Fujitsu MB90895 Series Hardware Manual page 158

CHAPTER 3 CPU
3.8.5.3 Timebase Timer Mode
The timebase timer mode operates only the oscillation clock (HCLK), sub clock (SCLK),
timebase timer, and watch timer. Peripherals other than the timebase timer and watch
timer stop.
I Timebase Timer Mode
The mode transits to the timebase timer mode when 0 is written to the TMD bit of the low-power
consumption mode control register (LPMCR) during operation in the PLL clock mode or the main clock
mode (CKSCR: SCM = 1).
G
Data retention function
In the timebase timer mode, data in the dedicated registers such as an accumulator and internal RAM are
held.
G
Operation when interrupt request generated
When an interrupt request is generated with the TMD bit of the low-power consumption mode control
register (LPMCR) set to "0", the mode does not transit to the timebase timer mode.If the CPU is not ready
to accept any interrupt request, the instruction next to the currently executing instruction is executed.If the
CPU is ready to accept any interrupt request, an interrupt operation immediately branches to the interrupt
processing routine.
G
Pin state
In the timebase timer mode, the input/output pins can be set to the high-impedance state or held in the state
before transiting to the timebase timer mode according to the setting of the SPL bit in the low-power
consumption mode control register (LPMCR).
Note: To set that pin to high impedance which serves either for a peripheral resource or as a port in
timebase timer mode, disable the output of the peripheral resource, then set the TMD bit to
"0".Listed below are applicable ports.This applies to the following pins: P14/PPG0, P15/
PPG1, P16/PPG2, P17/PPG3, P21/TOT0, P23/TOT1
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