External Interrupt Timing; Figure 3-1: External Interrupt Timing - Fujitsu ALL Series Application Note

3 External Interrupt Timing

The following figure shows timing of events for external interrupt. Here it is considered that
external interrupt pin INTn is configured to detect falling edge.
INTn
edge at
external
interrupt
Time required for CPU to finish the current instruction execution is dependent on type of
instruction being executed. If it is one of the interrupt deferring instructions / prefix codes then
it is definitely more than all other instructions. For further details please refer section 2.4.2 of
Interrupts application note MCU-AN-300210.
Time required for the context saving is dependent on various factors. Those are described in
section 2.4.1 of Interrupts application note MCU-AN-300210. The above mentioned time of 10
cycles is the minimum timing required for context saving.
MCU-AN -300203-E-V17
EXTERNAL INTERRUPTS
Chapter 3 External Interrupt Timing
200 ns
Time required
delay for
noise
filtering
External
First
interrupt
falling
recognized
by CPU
input

Figure 3-1: External Interrupt Timing

Minimum 10
CPU cycles
for CPU to
finish current
instruction
execution
CPU
finishes
current
interrupt
execution
and starts
context
saving
- 8 - © Fujitsu Microelectronics Europe GmbH
External
interrupt
for context ISR
saving execution
CPU starts
external
interrupt
ISR
execution