Fujitsu MB90895 Series Hardware Manual page 187

I Block Diagram of Pins of Port 2 (General-purpose I/O Port)
Port data register (PDR)
PDR read
PDR write
Port direction register (DDR)
DDR write
DDR read
Standby control Control of stop mode (SPL=1), timebase timer mode (SPL=1) and clock mode (SPL=1)
I Registers for Port 2
• The registers for port 2 are PDR2 and DDR2.
• The bits composing each register correspond to the pins of port 2 one-to-one.
Table 4.4-2 shows the correspondence between the registers and pins of port 2
Table 4.4-2 The correspondence between the registers and pins of port 2.
Port Name
port 2
Figure 4.4-1 Block Diagram of Pins of Port 2
Resource input
Output latch
Direction latch
Bits of Related Registers and Corresponding Pins
PDR2, DDR2
Corresponding pin
Resource output
Resource output
acceptance
Standby control (SPL=1)
bit7 bit6 bit5 bit4
P27 P26 P25 P24
CHAPTER 4 I/O PORT
Pch
Pin
Nch
bit3 bit2 bit1 bit0
P23 P22 P21 P20
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