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CHAPTER 10 8/16-bit PPG timer
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Operation in 16-bit PPG output operation mode
• When either PPG0 pin output or PPG1 pin output is enabled (PPGC0: PE0 = 1, PPGC1: PE1 = 1), the
same pulse wave is output from both the PPG0 and PPG1 pins.
• When a reload value is set in the PPG reload register (PRLL0/PRLH0, PRLL1/PRLH1) and a PPG timer
operation is also enabled (PPGC0:PEN0=1 and PPGC1:PEN1=1), the PPG down counter starts count
operation as a 16 - bit down counter (PCNT0 + PCNT1).
• To stop the count operation of the PPG down counters, disable the operation of the PPG timers of both
channels (PPGC0: PEN0 = 0 and PPGC1: PEN1 = 0).The count operation of the PPG down counter is
stopped and the output of the PPG output pin is held at a Low level.
• If the PPG1 down counter underflows, the reload values set in the PPG0 and PPG1 reload registers
(PRLL0/PRLH0 and PRLL1/PRLH1) are reloaded simultaneously to the PPG down counters (PCNT0 +
PCNT1).
• When an underflow occurs, the underflow generation flag bits in both channels are set simultaneously
(PPGC0: PUF0 = 1, PPGC1: PUF1 = 1). If an interrupt request is enabled at either channel (PPGC0:
PIE0 = 1, PPGC1: PIE1 = 1), an interrupt request is generated.
Notes:
• In the 16-bit PPG output operation mode, the underflow generation flag bits in the two
channels are set simultaneously when an underflow occurs (PPGC0: PUF0 = 1 and
PPGC1: PUF1 = 1).To prevent duplication of interrupt requests, disable either of the
underflow interrupt enable bits in the two channels (PPGC0: PIE0 = 0, PPGC1: PIE1 = 1
or PPGC0: PIE0 = 1, PPGC1: PIE1 = 0).
• If the underflow generation flag bits in the two channels are set (PPGC0: PUF0 = 0 and
PPGC1: PUF1 = 0), clear the two channels at the same time.
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