Fujitsu MB90895 Series Hardware Manual page 97

2
I Operation of EI
Figure 3.5-9 shows the operation of the EI
CPU
2
ISD :EI OS Descriptor
IOA :I/O address pointer
BAP :Buffer address pointer
ICS :EI2OS chanel selct bit of Interrupt control register (ICR)
DCT :Data counter
1. An interrupt request is generated and the EI
2. The interrupt controller selects the EI
3. The transfer-source and transfer-destination address pointers are read from the EI
4. Data is transferred according to the transfer-source and transfer-destination address pointers.
5. An interrupt factor is cleared automatically.
OS
Figure 3.5-9 Operation of EI
Memory space
By IOA
00 Bank area
(3)
ISD
(3)
By BAP
(4)
Buffer
2
OS.
2
OS
I/O area
Interrupt request
(2)
By ICS
Interrupt control register (ICR)
Interrupt controller
Count by DCT
2
OS is started.
2
OS descriptor.
CHAPTER 3 CPU
(5)
(1)
2
OS descriptor.
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