Receive-Interrupt Generation And Flag Set Timing - Fujitsu MB91150 Series Hardware Manual

CHAPTER 15 UART

15.6 Receive-Interrupt Generation and Flag Set Timing

The receive interrupts are interrupts indicating receive completion (SSR0-3: RDRF)
and receive-error generation (SSR0-3: PE, ORE, FRE).
I Receive-interrupt generation and flag set timing
When the stop bit is detected (in operation modes 0 to 4) or when the final bit (D7) of the data is
detected (in operation mode 2) during reception, the receive data is stored in input-data register
1 (SIDR0-3). In case of a receive error, the error flag (SSR0-3: PE, ORE, FRE) is set. After this,
the receive data full flag (SSR0-3: RDRF) is set to 1. In each mode, the SIDR0-3 value is invalid
when the error flag is 1.
❍ Operation mode 0 (asynchronous, normal mode)
When the stop bit is detected, the RDRF is set to 1. When a receive error occurs, the error flag
(PE, ORE, FRE) is set.
❍ Operation mode 1 (asynchronous, multiprocessor mode)
When the stop bit is detected, the RDRF is set to 1. When a receive error occurs, the error flag
(ORE, FRE) is set. Parity errors cannot be detected.
❍ Operation mode 2 (synchronous, normal mode)
When the final bit (D7) of receive data is detected, the RDRF is set to 1. If a receive error
occurs, the error flag (ORE) is set. Parity errors and framing errors cannot be detected. Figure
15.6-1 "Receive operation and flag set timing" shows the receive operation and flag set timing.
Receive data
(Operation mode 0)
Receive data
(Operation mode 1)
Receive data
(Operation mode 2)
PE, ORE, FRE*
RDRF
*: The PE flag cannot be used in mode 1.
The PE and FRE flags cannot be used in mode 2.
ST: Start bit
SP: Stop bit
A/D: Mode 2 (multiprocessor mode) address/data selection bit
❍ Timing of receive-interrupt generation
A receive-interrupt request is issued immediately after the RDRF, PE, ORE, or FRE flag is set to
1 while receive interrupts are enabled (SSR0-3: RIE = 1).
324
Figure 15.6-1 Receive operation and flag set timing
ST D0 D1
ST D0 D1
D0 D1
D5 D6 D7/P
SP
D6 D7 A/D
SP
D4 D5 D6
D7
Receive-interrupt generation