Communication Prescaler Control Register 0 (Cdcr0) - Fujitsu MB90895 Series Hardware Manual

14.3.5

Communication Prescaler Control Register 0 (CDCR0)

The communication prescaler control register 0 (CDCR0) is used to set the baud rate of
the dedicated baud rate generator for the UART0.
• Starts/stop the communication prescaler
• Sets the division ratio for machine clock
I Communication Prescaler Control Register 0 (CDCR0)
7
6 5
R/W
R/W : Read/Write
X : Undefined
: Unused
: Reset value
Table 14.3-5 Functions of Communication Prescaler Control Register
bit name
bit0 DIV3 to DIV0:
to Communication
bit3 prescaler division ratio
bits
bit4 Unused bits
to
bit6
bit7 MD:
Communication
prescaler control bit
Figure 14.3-7 Communication Prescaler Control Register
4 3 2 1 0
R/W R/W R/W R/W
bit3
DIV3 DIV2 DIV1
1
1
1
1
1
1
bit7
MD
0
1
• These bits set the machine clock division ratio.
Note:
When changing the division ratio, the time of at least two cycles of the division
clock should be allowed before the next communication is started in order to
stabilize the clock frequency.
Read: The value is undefined.
Write: No effect
The bit enables or disables the communication prescaler.
When the bit is set to "0": Operation stops.
When the bit is set to "1": Operation starts.
Reset value
0XXX1111
B
bit2 bit1 bit0
DIV0 Communication prescaler dividing ratio (div) bit
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
1
0 0 1
1
0 0 0
Communication prescaler control bit
Communication prescaler operating stop
Communication prescaler operating enabled
Function
CHAPTER 14 UART0
Setting disabled
Dividing by 2
Dividing by 3
Dividing by 4
Dividing by 5
Dividing by 6
Dividing by 7
Dividing by 8
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