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CHAPTER 14 UART0
G
Division ratio based on communication prescaler (common between asynchronous and clock
synchronous modes)
The frequency divide ratio of the machine clock is set by the divide ratio select bits (CDCR0: DIV3 to
DIV0) in the communication prescaler control register.
Table 14.5-1 Division Ratio Based on Communication Prescaler
Machine
clockφ(MHz)
div: Division ratio based on communication prescaler
G
Baud Rate (Asynchronous Mode)
The baud rate in asynchronous/clock-synchronous mode is generated by dividing the output clock
frequency of the communication prescaler by 2, 4, 8, 16, or 32.The divide ratio is set by the clock input
source select bits (SMR0: CS2 to CS0).
Table 14.5-2 Baud Rate (Asynchronous Mode)
Baud rate selection bit
CS2
CS1
0
0
0
0
0
1
0
1
1
0
φ
:Machine clock
div: Division ratio based on communication prescaler
408
Divide
ratio
div
4
4
6
6
8
8
6
3
8
4
10
5
12
6
14
7
16
8
8
2
12
3
16
4
16
2
φ
CS0
/div=2MHz
0
9,615
1
4,808
0
2,404
1
1,202
0
31,250
Communication Prescaler Control
Register
(CDCR0)
DIV3
DIV2
DIV1
1
1
0
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
1
0
0
1
0
0
1
1
1
1
1
0
1
1
0
1
1
1
Baud Rate (bps)
φ
φ
/div=4MHz
/div=8MHz
19,230
38,460
9,615
19,230
4,808
9,615
2,404
4,808
62,500
Division result
φ/div
(MHz)
DIV0
0
0
1
0
1
0
1
2
0
1
0
0
1
4
0
0
8
Calculation
φ
(
/ div) / (8
φ
(
/ div) / (8
φ
(
/ div) / (8
φ
(
/ div) / (8
φ
-
(
/ div) /2
×
×
13
2)
×
×
2
13
2
)
×
×
3
13
2
)
×
×
4
13
2
)
6
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