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CHAPTER 15 UART1
15.2
Block Diagram of UART1
The UART1 consists of the following block.
I Block Diagram of UART1
Dedicated baud
rate generator
16-bit
reload timer
Pin
SCK1
Pin
SIN1
Reception state
judge circuit
Communi-
cation
prescaler
control
register
432
Figure 15.2-1 Block Diagram of UART1
Control bus
Clock
Reception
selector
Reception
clock
control
circuit
Start bit
detection circuit
Reception bit
counter
Reception parity
counter
Shift register
for reception
Serial input
data register 1
Internal data bus
MD1
MD0
Serial
MD
CS2
mode
CS1
register
CS0
DIV2
RST
1
DIV1
SCKE
DIV0
SOE
Transmission
clock
Transmission
control
circuit
Transmission
start circuit
Transmission
bit counter
Transmission
parity counter
Shift register
for transmission
Reception
finish
Serial output
data register 1
PEN
P
Serial
SBL
control
CL
register
A/D
REC
1
RXE
TXE
Reception
interrupt
request output
Transmission
interrupt
request output
Pin
SOT1
Transmission start
Reception error
generating signal
2
for EI
OS (to CPU)
PE
ORE
Serial
FRE
status
RDRF
register
TDRE
BDS
1
RIE
TIE
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