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CHAPTER 3 CPU
G
Return by interrupt
When an interrupt request higher than the interrupt level (IL) of 7 is generated from external interrupt in the
stop mode, the stop mode is cancelled.In the stop mode, the main clock oscillation stabilization wait time or
the sub clock oscillation stabilization wait time is generated after the stop mode is cancelled. After the stop
mode is cancelled, as with normal interrupt processing, the generated interrupt request is identified
according to the settings of the I flag in the condition code register (CCR), the interrupt level mask register
(ILM), and the interrupt control register (ICR).
• When the CPU is not ready to accept any interrupt request, the instruction next to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt
processing routine.
Note:
When handling an interrupt, the CPU usually services the interrupt after executing the
instruction that follows the one specifying the stop mode.
In PLL stop mode, the main clock and PLL multiplier circuit remain stopped. When the CPU
returns from PLL stop mode, therefore, it is necessary to allow for the main clock oscillation
stabilization wait time and PLL clock oscillation stabilization wait time to be held. In this
case, the oscillation stabilization wait times for the main clock and PLL clock are counted
simultaneously according to the value specified in the oscillation stabilization wait time
select bits (CKSCR: WS1, WS0) in the clock select register. The CKSCR: WS1/WS0 bits
must therefore be set to a value according to the main clock or PLL clock oscillation
stabilization wait time, whichever is longer. The PLL clock requires an oscillation
stabilization wait time of at least 2
selection bits (CKSCR: WS1, WS0) in the clock selection register to "10
144
14
/HCLK. Set the oscillation stabilization wait time
" or "11
".
B
B
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