Fujitsu MB90895 Series Hardware Manual page 146

CHAPTER 3 CPU
G
CPU intermittent operation selector
This selector selects the halt cycle count of the CPU clock in the CPU intermittent operation mode.
G
Standby controller
The CPU clock controller and resource clock controller switch between the CPU operating clock and
resource operating clock to enter and cancel the standby mode.
G
CPU clock controller
This controller supplies an operating clock to the CPU.
G
Pin high-impedance controller
This controller causes the input/output pins to become high impedance in the watch mode, timebase timer
mode, and stop mode.
G
Internal reset generator
This generator generates the internal reset signal.
G
Low-power consumption mode control register (LPMCR)
This register transits a clock mode to, and cancels the standby mode, and sets the CPU intermittent
operation mode.
Note: There is no sub-clock in MB90F897S.
128