Fujitsu MB90895 Series Hardware Manual page 559

• The message buffers should be arranged in order of ascending number (x) as follows;
- Smallest number (x): Acceptance mask set to full-bit comparison
- Middle number (x): Acceptance mask registers 0 and 1 used
- Largest number (x): Acceptance mask set to "full-bit masking"
G
setting acceptance mask select register
Table 16.5-1 Setting acceptance mask select register
AMSx.1
0
0
1
1
Figure 16.5-3 Flowchart of Determining Message Buffer that Stores Received Message
Message is not received (RCR : RCx=0),
or any message buffer set to "full-bit comparison"
(AMSR : AMSx.1=0, AMSx.0=0)?
Select the smallest-numbered message
buffer (X) from message buffers
corresponding to the above.
AMSx.0
0 Full-bit comparison is performed.
1 Full-bit masking is performed.
0 Using acceptance mask register 0 (AMR0)
1 Using acceptance mask register 1 (AMR1)
Start
Yes
Finish
CHAPTER 16 CAN controller
Acceptance mask (x=7 to 0)
No
Select one of the smallest
message buffer number (X)
541