Fujitsu MB90895 Series Hardware Manual page 166

CHAPTER 3 CPU
G
Oscillation stabilization wait time of sub clock
In the sub-stop mode, the oscillation of the sub clock stops and the oscillation stabilization wait time of the
sub clock is required.The oscillation stabilization wait time of the sub clock is fixed at 2
sub clock).
G
Oscillation stabilization wait time of PLL clock
In main clock mode, the PLL multiplier circuit remains stopped. When the CPU enters the PLL clock
mode, therefore, it is necessary to allow for the PLL clock oscillation stabilization wait time.The CPU runs
in main clock mode till the PLL clock oscillation stabilization wait time has elapsed.The PLL clock
oscillation stabilization wait time taken when the clock mode is switched from main clock to PLL clock is
fixed at 2
In subclock mode, the main clock and PLL multiplier circuit remain stopped. When the CPU enters the
PLL clock mode, therefore, it is necessary to allow for the main clock oscillation stabilization wait time and
PLL clock oscillation stabilization wait time. In this case, the oscillation stabilization wait times for the
main clock and PLL clock are counted simultaneously according to the value specified in the oscillation
stabilization wait time select bits (CKSCR: WS1, WS0) in the clock select register. The CKSCR: WS1/
WS0 bits must therefore be set to a value according to the main clock or PLL clock oscillation stabilization
wait time, whichever is longer. The PLL clock requires an oscillation stabilization wait time of at least 2
HCLK. For switching to PLL clock mode, therefore, set the CKSCR: WS1 and WS0 bits to "10
In PLL stop mode, the main clock and PLL multiplier circuit remain stopped. When the CPU returns from
PLL stop mode, therefore, it is necessary to allow for the main clock oscillation stabilization wait time and
PLL clock oscillation stabilization wait time. In this case, the oscillation stabilization wait times for the
main clock and PLL clock are counted simultaneously according to the value specified in the oscillation
stabilization wait time select bits (CKSCR: WS1, WS0) in the clock select register. The CKSCR: WS1/
WS0 bits must therefore be set to a value according to the main clock or PLL clock oscillation stabilization
wait time, whichever is longer. The PLL clock requires an oscillation stabilization wait time of at least 2
HCLK. Set the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection
register to "10
I Transition of Clock Mode
While the clock mode is being switched, do not switch the CPU to low power consumption mode or to any
other clock mode until the current process of mode switching is completed.Check the MCM and SCM bits
in the clock select register (CKSCR) to make sure that the transition to the new clock mode has been
completed. If the mode is switched to another clock mode or low power consumption mode before
completion of switching, the mode may not be switched.
Note: There is no sub-clock in MB90F897S.
148
14
/HCLK (HCLK: oscillation clock).
" or "11 ".
B B
14
/SCLK (SCLK:
14
/
" or "11 ".
B B
14
/