Fujitsu MB90895 Series Hardware Manual page 127

I Clock Supply Map
Machine clocks generated by the clock generation section are supplied as operating clocks of the CPU and
peripherals. The operation of the CPU and peripheral peripherals is affected by switching between the main
clock and subclock or PLL clock (clock mode) or by switching the PLL clock multiplier. The clock-
divided output of the timebase timer is supplied to some peripherals, and the operating clock can be
selected for each peripheral.
Figure 3.7-1 shows the clock supply map.
Clock generator
X0A
Pin
Sub clock
X1A generator
Pin
X0
Pin
Oscillation
X1
clock
Pin generator
HCLK: Oscillation clock
PCLK: PLL clock
SCLK: Sub clock
: Machine clock
Figure 3.7-1 Clock Supply Map
Watch timer
Time base timer
1 2 3 4
PLL multiplying circuit
SCLK PCLK
2/4-frequency
division
2-frequency
Clock selector
division
HCLK
MCLK
CPU Intermittent
Peripheral functions
4
4 Watchdog timer
8/16 bit
PPG timer 0,1
8/16 bit
PPG timer 2,3
16 bit
reload timer 0
Communication prescaler 1
UART1
operation
CPU
16-bit
reload timer 1
8/10-bit
A/D converter
Input capture
unit
16-bit
free-run-timer
CAN controller
3
Oscillation
stabilization waiting time
CHAPTER 3 CPU
PPG0,1
Pin
PPG2,3
Pin
TIN0
Pin
TOT0
Pin
SCK1
Pin
SOT1
Pin
SIN1
Pin
TIN1
Pin
TOT1
Pin
ADTG
Pin
IN0,1,2,3
Pin
RX
Pin
TX
Pin
109