Acceptance Mask Select Register (Amr) - Fujitsu MB90895 Series Hardware Manual

16.3.19

Acceptance Mask Select Register (AMR)

The CAN controller contains two acceptance mask registers (AMR0 and AMR1), each of
which can be used in the standard frame format (ID11 bits, AM28 to AM18) and the
extended frame format (ID29 bits, AM28 to AM0).
I Acceptance Mask Select Register (AMSR)
BYTE0
BYTE1
BYTE2
BYTE3
R/W
X : Undefined
−
: Unused
Figure 16.3-27 Acceptance Mask Select Register (AMSR)
bit7 6 5
AM28 AM27 AM26
R/W R/W R/W
bit15 14 13
AM20 AM19 AM18
R/W R/W R/W
bit7 6 5
AM12 AM11 AM10
R/W R/W R/W
15 14 13
AM4 AM3 AM2
R/W R/W R/W
Read/Write
: Standard frame format uses in bit
4 3 2 1
AM25 AM24 AM23 AM22
R/W R/W R/W R/W
12 11 10 9
AM17 AM16 AM15 AM14
R/W R/W R/W R/W
4 3 2 1
AM9 AM8 AM7 AM6
R/W R/W R/W R/W
12 11 10 9
AM1 AM0
R/W R/W
CHAPTER 16 CAN controller
0 Reset value
AM21
X X X X X X X X
B
R/W
8
Reset value
AM13
X X X X X X X X
B
R/W
0 Reset value
AM5
X X X X X X X X
B
R/W
8 Rsest value
X X X X X X X X
B
525