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16.3.8
Transmit request register (TREQR) ............................................................................................ 503
16.3.9
Transmit RTR register (TRTRR) ................................................................................................. 505
16.3.10 Remote frame receive waiting register (RFWTR) ....................................................................... 507
16.3.11 Transmission cancel register (TCANR) ...................................................................................... 509
16.3.12 Transmit complete register (TCR) .............................................................................................. 511
16.3.13 Transmit complete interrupt enable register (TIER) ................................................................... 513
16.3.14 Receive complete register (RCR) ............................................................................................... 515
16.3.15 Receive RTR register (RRTRR) ................................................................................................. 517
16.3.16 Receive overrun register (ROVRR) ............................................................................................ 519
16.3.17 Receive complete interrupt enable register (RIER) .................................................................... 521
16.3.18 Acceptance mask select register (AMSR) .................................................................................. 523
16.3.19 Acceptance Mask Select Register (AMR) .................................................................................. 525
16.3.20 Message Buffers ......................................................................................................................... 527
16.3.21 ID Register (IDRx, x = 7 to 0) ..................................................................................................... 528
16.3.22 DLC Register (DLCR) ................................................................................................................. 531
16.3.23 Data Register (DTR) ................................................................................................................... 532
16.4
Interrupts of CAN Controller ............................................................................................................ 533
16.5
Explanation of Operation of CAN Controller .................................................................................... 535
16.5.1
Transmission .............................................................................................................................. 536
16.5.2
Reception ................................................................................................................................... 539
16.5.3
Procedures for Transmitting and Receiving ............................................................................... 543
16.5.4
Setting Multiple Message Reception .......................................................................................... 550
16.6
Precautions when Using CAN Controller ......................................................................................... 552
16.7
Program Example of CAN Controller ............................................................................................... 553
CHAPTER 17 Address Match Detecting Function ........................................................ 555
17.1
Overview of Address Match Detection Function .............................................................................. 556
17.2
Block Diagram of Address Match Detection Function ..................................................................... 557
17.3
Configuration of Address Match Detection Function ....................................................................... 558
17.3.1
Address detection control register (PACSR) .............................................................................. 559
17.3.2
Detect address setting registers (PADR0, PADR1) .................................................................... 561
17.4
Explanation of Operation of Address Match Detection Function ..................................................... 563
17.4.1
Example of using Address Match Detection Function ................................................................ 564
17.5
Program Example of Address Match Detection Function ................................................................ 569
CHAPTER 18 ROM Mirroring Function Selection Module ........................................... 571
18.1
Overview of ROM Mirroring Function Selection Module.................................................................. 572
18.2
ROM Mirroring Function Selection Register (ROMM) ..................................................................... 574
CHAPTER 19 512 KBIT FLASH MEMORY .................................................................... 575
19.1
Overview of 512 Kbit Flash Memory ............................................................................................... 576
19.2
Registers and Sector/Bank Configuration of Flash Memory ........................................................... 577
19.3
Flash Memory Control Status Register (FMCS) ............................................................................. 579
19.4
Flash Memory Write Control Register (FWR0/1) ............................................................................ 582
19.5
How to Start Automatic Algorithm of Flash Memory ....................................................................... 586
19.6
Reset Vector Addresses in Flash Memory ..................................................................................... 589
19.7
Check the Execution State of Automatic Algorithm ........................................................................ 590
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