Fujitsu MB90895 Series Hardware Manual page 412

CHAPTER 14 UART0
Table 14.3-4 Function of Serial Status Register 0 (SSR0)
bit name
bit8 TIE:
Transmission interrupt
enable bit
bit9 RIE:
Interrupt enable bit
bit10 Unused bits
bit11 TDRE:
Transmit data write flag
bit
bit12 RDRF:
Receive data load flag bit
bit13 FRE:
flaming error flag bit
bit14 ORE:
Overrun error flag bit
bit15 PE:
parity error flag bit
394
Enable or disable send interrupt.
When the bit is set to "1": A transmission interrupt request is generated when
the data written to serial output data register 0 is transmitted to the send shift
register (SSR0:TDRE=1).
Enable or disable receive data.
When the bit is set to "1": A reception interrupt request is generated either
when received data is loaded to serial input data register 0 (SSR0: RDRF = 1)
or when a reception error occurs (SSR0: PE = 1, DRE = 1, or FRE = 1).
Read: The value is undefined.
Write: No effect
Show the status of the serial output data register 0.
• The flag is cleared to "0" when transmit data is written to serial output data
register 0 (SODR0).
• This bit is set to "1" when data is loaded to the send shift register and
transmission starts.
• A transmission interrupt request is generated when the transmit data written to
serial output data register 0 (SODR0) is transferred to the transmission shift
register with transmission interrupts enabled (SSR0: TIE = 1).
Show the status of the serial input data register 0.
• When received data is loaded to serial input data register 0 (SSR0), the receive
data load flag bit (SSR0: RDRF) is set to "1".
• The bit is cleared to 0 when data is read from serial input register 0 (SIDR0).
• When reception interrupts have been enabled (SSR0: RIE = 1), a reception
interrupt request is generated if received data is loaded into the serial input data
register (SIDR0).
Detect a framing error in receive data.
• This bit is set to "1" when a framing error occurs.
• The flag is cleared by writing "0" to the reception error flag clear bit (SCR0:
REC).
• When reception interrupts have been enabled (SSR0: RIE = 1), a reception
interrupt request is generated if a framing error occurs.
• When the framing error flag bit is set (SSR0: FRE = 1), data in serial input data
register 0 is made invalid.
Detect an overrun error in receiving.
• This bit is set to "1" when an overrun error occurs.
• The flag is cleared by writing "0" to the reception error flag clear bit (SCR0:
REC).
• When reception interrupts have been enabled (SSR0: RIE = 1), a reception
interrupt request is generated if an overrun error occurs.
• When the overrun error flag bit is set (SSR0: ORE = 1), data in serial input data
register 0 is made invalid.
Detect an overrun error in receiving.
• This bit is set to "1" when a parity error occurs.
• The flag is cleared by writing "0" to the reception error flag clear bit (SCR0:
REC).
• When reception interrupts have been enabled (SSR0: RIE = 1), a reception
interrupt request is generated if a parity error occurs.
• When the parity error flag bit is set (SSR0: PE = 1), data in serial input data
register 0 is made invalid.
Function