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APPENDIX
Table A.8-4 12 Increment/decrement instructions (byte, word, long word)
Mnemonic
INC
ear
INC
eam
DEC
ear
DEC
eam
INCW
ear
INCW
eam
DECW
ear
DECW
eam
INCL
ear
INCL
eam
DECL
ear
DECL
eam
Note:
See Table A.5-1 "Execution cycle counts in each addressing mode" and Table A.5-2 "Cycle count
correction values for counting execution cycles" for information on (a) to (d) in the table.
Table A.8-5 11 Compare instructions (byte, word, long word)
Mnemonic
CMP
A
CMP
A,ear
CMP
A,eam
CMP
A,#imm8
CMPW
A
CMPW
A,ear
CMPW
A,eam
CMPW
A,#imm16
CMPL
A,ear
CMPL
A,eam
CMPL
A,#imm32
Note:
See Table A.5-1 "Execution cycle counts in each addressing mode" and Table A.5-2 "Cycle count
correction values for counting execution cycles" for information on (a) to (d) in the table.
644
#
RG
2
3
2
0
2+
5+(a)
0
2 x (b)
2
3
2
0
2+
5+(a)
0
2 x (b)
2
3
2
0
2+
5+(a)
0
2 x (c)
2
3
2
0
2+
5+(a)
0
2 x (c)
2
7
4
0
2+
9+(a)
0
2 x (d)
2
7
4
0
2+
9+(a)
0
2 x (d)
#
RG
1
1
0
0
2
2
1
0
2+
3+(a)
0
(b)
2
2
0
0
1
1
0
0
2
2
1
0
2+
3+(a)
0
(c)
3
2
0
0
2
6
2
0
2+
7+(a)
0
(d)
5
3
0
0
B
Operation
byte (ear) <-- (ear) + 1
byte (eam) <-- (eam) + 1
byte (ear) <-- (ear) - 1
byte (eam) <-- (eam) - 1
word (ear) <-- (ear) + 1
word (eam) <-- (eam) + 1
word (ear) <-- (ear) - 1
word (eam) <-- (eam) - 1
long (ear) <-- (ear) + 1
long (eam) <-- (eam) + 1
long (ear) <-- (ear) - 1
long (eam) <-- (eam) - 1
B
Operation
byte (AH) - (AL)
byte (A) - (ear)
byte (A) - (eam)
byte (A) - imm8
word (AH) - (AL)
word (A) - (ear)
word (A) - (eam)
word (A) - imm16
long (A) - (ear)
long (A) - (eam)
long (A) - imm32
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