Fujitsu MB90895 Series Hardware Manual page 139

(1) MCS bit "0" write
(2) Termination of PLL clock oscillation stabilization wait time & CS1,CS0=00
(3) Termination of PLL clock oscillation stabilization wait time & CS1,CS0=01
(4) Termination of PLL clock oscillation stabilization wait time & CS1,CS0=10
(5) Termination of PLL clock oscillation stabilization wait time & CS1,CS0=11
(6) MCS bit "1" write (include hardwarestandby and watchdogreset)
(7) Synchronous timin of PLL clock and main clock
(8) SCS bit "0" write
(9) Terminate of sub clock oscillration stabilization wait time (2
(10) SCS bit "1" write
(11) Termination of main clock oscillation stabilization wait time
(12) Termination of main clock oscillation stabilization wait time & CS1,CS0=00
(13) Termination of main clock oscillation stabilization wait time & CS1,CS0=01
(14) Termination of main clock oscillation stabilization wait time & CS1,CS0=10
(15) Termination of main clock oscillation stabilization wait time & CS1,CS0=11
(16) SCS bit "1" write, MCS bit"0" wreit
(17) Synchronous timing of PLL clock and ub ckock
MCS : PLL clock selector bit of Clock selecter register (CKSCR)
MCM : PLL clock indicate bit of Clock selecter register (CKSCR)
SCS : Sub clock selector bit of Clock selecter register (CKSCR)
SCM : Sub clock indicate bit of Clock selecter register (CKSCR)
CS1,CS0 : Multiprecation selecter bit of Clock selecter register (CKSCR)
Notes: • The reset value of the machine clock is in the main clock mode (MCS = 1, SCS = 1)
• When SCS and MCS are both "0", SCS is preferred, and the sub clock is selected.
• For switching from subclock mode to PLL clock mode, set the oscillation stabilization
wait time select bits (WS1, WS0) in the CKSCR register to "10
• There is no sub-clock in MB90F897S.
14
/SCLK)
" or "11 ".
B B
CHAPTER 3 CPU
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