Message Buffers - Fujitsu MB90895 Series Hardware Manual

16 bit, controller manual
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16.3.20

Message Buffers

The message buffers consist of ID register, DLC register, and data register and are used
for transmission/reception of messages.
I Message Buffers
• There are 8 message buffers.
• One message buffer x (x = 0 to 7) consists of the ID register (IDRx), DLC register (DLCRx), and data
register (DTRx).
• The message buffer (x) is used to transmit and receive messages.
• Higher priority is given to smaller number message buffer.
- At transmission, if a transmit request is generated to more than one message buffer, transmission is
started with the message buffer with the smallest number.
- At receiving, if the received message ID passes the acceptance filter (which compares received
message ID with message buffer ID after acceptance masking) set in more than one message buffer,
the received message is stored in the message buffer with the smallest number.
• If the same acceptance filter is set in more than one message buffer, it can be used as multiple message
buffers.This provides sufficient time to perform receiving.
Notes:
1) Write by words to the message buffer area and general-purpose RAM area. At writing by
bytes, undefined data is written to the upper bytes when writing to the lower bytes is
performed. Writing to the upper bytes is ignored.
2) The message buffer (x) area disabled by the message buffer enable register (BVALR:
BVALx = 0) can be used as a general-purpose RAM area. However, during transmitting
or receiving, it may take up to 64 machine cycles to access the message buffer area and
general - purpose RAM area.
Reference:
• For details on transmission, see 16.5.1 Transmission.
• For details on reception, see 16.5.2 Reception.
• See 16.5.4 Setting Multiple Message Receiving for details of the configuration of the
multiple message buffer.
CHAPTER 16 CAN controller
527

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