Receive Interrupt Generation And Flag Set Timing - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 21 UART
21.5.1

Receive Interrupt Generation and Flag Set Timing

Interrupts during reception are one generated upon completion of reception (SSR0 to
SSR3: RDRF) and one generated upon occurrence of a reception error (SSR0 to SSR3:
PE, ORE, FRE).
Receive Interrupt Generation and Flag Set Timing
When data is received, it is stored in serial input data register 0 to 3 (SIDR0 to SIDR3) upon detection of
the stop bit (in operation mode 0 or 1) or of the data's last bit (SIDR0 to SIDR3: D7) (in operation mode 2).
When a receiving error occurs, an error flag (SSR0 to SSR3: PE, ORE, FRE) is set, a receiving data full
flag (SSR0 to SSR3: RDRF) is set. If any of the flags is set to the each operation mode, the serial input data
registers 0 to 3 (SIDR0 to SIDR3) that have received are invalid.
Operation mode 0 (Asynchronous normal mode)
The receiving data full flag (SSR0 to SSR3: RDRF) is set on detection of the stop bit. When a reception
occurs, the error flag (SSR0 to SSR3: PE, ORE, FRE) is set.
Operating mode 1 (asynchronous multiprocessor mode)
The receiving data full flag bit (SSR0 to SSR3: RDRF) is set when the stop bit is detected. When a
reception error occurs, the error flag (SSR0 to SSR3: ORE, FRE) is set. But parity errors (SSR0 to
SSR3:PE) cannot be detected.
Operation mode 2 (clock synchronizer normal mode)
When the last bit (SIDR0 to SIDR3: D7) of the receiving data is detected, the receiving data full flag bit
(SSR0 to SSR3: RDRF) is set. When a reception error occurs, the error flag (SSR0 to SSR3:ORE) is set.
Neither a parity error (SSR0 to SSR3:PE) nor a framing error (SSR0 to SSR3:FRE) can be detected.
Figure 21.5-1 shows the timing of receiving operation and the set of flags.
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