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G
Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure A.4-4 Example of long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H
Before execution
After execution
G
Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program bank register (PCB). Note that the operand
address of each of the following instructions is not deemed to be (next instruction address + disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure A.4-5 Example of program counter indirect addressing with offset (@PC + disp16)
MOVW A, @PC+20H
Before execution
After execution
(This instruction reads data by long register indirect addressing with an
offset and stores it in A.)
A
0 7 1 6
2 5 3 4
RL2
F 3 8 2 4 B 0 2
A
2 5 3 4
F F E E
RL2
F 3 8 2 4 B 0 2
(This instruction reads data by program counter indirect addressing with a
offset and stores it in A.)
A
0 7 1 6
2 5 3 4
PCB
C 5
PC
4 5 5 6
A
2 5 3 4
F F E E
PCB
C 5
PC
4 5 5 A
APPENDIX A Instructions
Memory space
824B28H
F F
E E
824B27H
(+25H)
Memory space
C5457BH
F F
C5457AH
E E
C5455AH
+20H
C54559H
0 0
+4
C54558H
2 0
C54557H
9 E
C54556H
7 3
MOVW
A, @PC+20H
629
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