Fujitsu MB90895 Series Hardware Manual page 138

CHAPTER 3 CPU
Figure 3.7-6 shows the transition of a clock mode.
Main
MCS=1
MCM=1
SCS=1
SCM=1
CS1,CS0=xx
120
Figure 3.7-6 Clock Mode Transition
(8)
(10)
(1)
(11)
(6)
→
(2)
Main PLLx
MCS=0
(3)
MCM=1
(4)
SCS=1
(5)
SCM=1
CS1,CS0=xx
→
PLL1 Main
MCS=1
(7)
MCM=0
SCS=1
(6)
SCM=1
CS1,CS0=00
→
PLL2 Main
MCS=1
(7)
MCM=0
SCS=1
(6)
SCM=1
CS1,CS0=01
→
PLL3 Main
MCS=1
(7)
MCM=0
SCS=1
(6)
SCM=1
CS1,CS0=10
→
PLL4 Main
MCS=1
(7)
MCM=0
SCS=1
(6)
SCM=1
CS1,CS0=11
→
Main Sub
MCS=1
MCM=1
(9)
SCS=0
SCM=1
CS1,CS0=xx
→
Sub Main
MCS=1 (8)
MCM=1
SCS=1
SCM=0
(12)
CS1,CS0=xx Sub
MCS=0
(13)
MCM=1
(14)
SCS=1
(15)
SCM=0
CS1,CS0=xx
PLL1 mutiplier PLL1
MCS=0 MCS=1
MCM=0 MCM=0
SCS=1 SCS=0
(8)
SCM=1 SCM=1
CS1,CS0=00 CS1,CS0=00
PLL2 mutiplier PLL2
MCS=0 MCS=1
MCM=0 MCM=0
SCS=1 SCS=0
(8)
SCM=1 SCM=1
CS1,CS0=01 CS1,CS0=01
PLL3
PLL3 mutiplier
MCS=1
MCS=0
MCM=0
MCM=0
SCS=0
SCS=1
(8)
SCM=1
SCM=1
CS1,CS0=10
CS1,CS0=10
PLL4 mutiplier PLL4
MCS=0 MCS=1
MCM=0 MCM=0
SCS=1 SCS=0
(8)
SCM=1 SCM=1
CS1,CS0=11 CS1,CS0=11
Sub
MCS=1
MCM=1
(16)
SCS=0
(10)
SCM=0
CS1,CS0=xx
(8)
→
PLL
→
Sub
(17)
→
Sub
(17)
→
Sub
(17)
→
Sub
(17)