Fujitsu MB90895 Series Hardware Manual page 507

Table 16.3-3 Functions of Control Status Register (Low) (CSR: L) (1/2)
bit name
bit0 HALT: This bit controls the bus halt.The halt state of the bus can be checked by reading the HALT bit.
Bus halt bit At reading
"0": on bus operation
"1": halting bus operation
At writing
"0": cancels bus halt
"1":set bus halt
Note: When write 0 to this bit during the node status is Bus Off, ensure that 1 is written to this bit.
Reference programming example:
switch (IO_CANCT0.CSR.bit.NS)
{
case 0:/* error active */
case 1:/* warning */
case 2:/* error passive */
default:/* bus off */
}
*: The valiable i is used for fail safe.
[Conditions for halting bus]
•
•
•
[Operation when bus halted]
Message being transmitted: Bus halted after completion of transmitting
Message being receiving: Bus halted immediately
Storing in message buffer: Bus halted after completion of storing
Note:
•
•
[Conditions for canceling bus halt]
•
•
•
Note: When write 0 to this bit during the node status is Bus Off, ensure that 1 is written to this bit.
[State in which bus halted]
•
•
•
Note:
•
bit1 Reserved: Be sure to set this bit to "0".
reserved bit Read: "0" is always read.
break;
break;
break;
for (i=0; (i<= 500) || (IO_CANCT0.CSR.bit.HALT= 0):i++);
IO_CANCT0.CSR.word = 0x0084; /* halt = 0 */
Hardware reset
Node status transition to bus off
Writing "1" to HALT bit
To check whether the bus is halted, read the value of the HALT bit.
Before switching to the low power consumption mode, write "1" to the HALT bit and then read the HALT bit
to check that the bus is completely halted (CSR: HALT = 1).
The state in which the bus is halted by a hardware reset or by writing "1" to the HALT bit is cancelled after 0
is written to the HALT bit and an 11-bit High level (receive) is input continuously to the receive input pin
(RX).
The state in the bus off is cancelled after "0" is written to the HALT bit and an 11-bit High level (receive) is
input continuously 128 times to the receive input pin (RX).
The values of the transmit and receive error counters are both returned to "0" and the node status transits to
error active.
Transmitting and receiving are not performed.
A High level (receive) is output to the transmit output pin (TX).
Other registers or error counters are not updated.
Set the bit timing register (BTR) after halting the bus.
CHAPTER 16 CAN controller
Function
489