Fujitsu MB90895 Series Hardware Manual page 371

G
Decoder
This decoder sets the A/D conversion start channel select bits and the A/D conversion end channel select
bits in the A/D control status register (ADCS: ANS2 to ANS0 and ANE2 to ANE0) to select the analog
input pin to be used for A/D conversion.
G
Analog channel selector
This selector selects the pin to be used for A/D conversion from the 8-channel analog input pins by
receiving a signal from the decoder.
G
Sample & hold circuit
This circuit holds the input voltage selected by the analog channel selector. By holding the input voltage
immediately after A/D conversion is started, A/D conversion is performed without being affected by the
fluctuation of the input voltage during A/D conversion.
G
D/A converter
This converter generates the reference voltage which is compared with the input voltage held in the sample
& hold circuit.
G
Comparator
This comparator compares the D/A converter output voltage with input voltage held in the sample & hold
circuit to determine the mount of voltage.
G
Control circuit
This circuit determines the A/D conversion value by receiving the signal indicating the amount of voltage
determined by the comparator.When the A/D conversion results are determined, the result data is stored in
the A/D data register.If an interrupt request is enabled, an interrupt is generated.
CHAPTER 13 8/10-bit A/D converter
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