Serial Input Data Register 1 (Sidr1) And Serial Output Data Register 1 (Sodr1) - Fujitsu MB90895 Series Hardware Manual

CHAPTER 15 UART1
15.3.4 Serial Input Data Register 1 (SIDR1) and Serial Output
Data Register 1 (SODR1)
The serial input data register and serial output data register are allocated to the same
address.At read, the register functions as SIDR1. At write, the register functions as
SODR.
I Serial input data register 1 (SIDR1)
R : Read only
X : Undefined
SIDR1 is a data buffer register for receiving serial data.
• The serial data signal transmitted to the serial input pin (SIN1) is converted by the shift register and
stored in SIDR1.
• When the data length is 7 bits, the upper one bit (SIDR1: D7) becomes invalid.
• When receive data is stored in the serial input data register 1 (SIDR1), the receive data load flag bit
(SSR1 register bit 12: RDRF) is set to "1".When a receive interrupt is enabled (SSR1 register bit 9: RIE
= 1), a receive interrupt request is issued.
• Read SIDR1 when the receive data load flag bit (SSR1 register bit 12: RDRF) is set to "1".The receive
data load flag bit (SSR1 register bit 12: RDRF) is cleared to 0 automatically when SIDR1 is read.
• When a receive error occurs (any one of SSR1 register bit 15, 14, 13: PE, ORE and FRE is "1"), the
receive data in SIDR1 becomes invalid.
444
Figure 15.3-5 Serial input data register 1 (SIDR1)
bit7 6
D7 D6 D5
R R
5 4 3 2 1
D4 D3 D2 D1
R R R R R
bit0
Reset value
D0 XXXXXXXX
B
R