Fujitsu MB90895 Series Hardware Manual page 653

Table A.5-2 Cycle Count Correction Values for Counting Execution Cycles
Operand
Internal register
Internal memory Even
address
Internal memory Odd
address
External data bus 16-
*2
bit even address
External data bus 16-
*2
bit odd address
External data bus 8-
*2
bits
*1:(b), (c), and (d) are used for (cycle count) and B (correction value) in A.8 F
List.
*2:When an external data bus is used, the number of cycles during which an instruction is made to wait
by ready-signal input or automatic ready must also be added.
Table A.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Instruction
Internal memory
External data bus 16-bits
External data bus 8-bits
When an external data bus is used, the number of cycles during which an instruction is made to wait by
ready-signal input or automatic ready must also be added.
As every instruction fetch does not delay instruction execution, in practice, the correction values should
be used to calculate the worst case.
*1
(b) byte
Cycle Access Cycle
count count count
+0 1 +0
+0 1 +0
+0 1 +2
+1 1 +1
+1 1 +4
+1 1 +4
Byte boundary
−
−
+3
APPENDIX A Instructions
*1
(c) word (d) long
Access Cycle
count count
1 +0
1 +0
2 +4
1 +2
2 +8
2 +8
2
MC-16LX Instruction:
Word boundary
+2
+3
−
*1
Access
count
2
2
4
2
4
4
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