Fujitsu MB90895 Series Hardware Manual page 91

I Operation of Hardware Interrupt
Figure 3.5-6 shows the operation from the generation of hardware interrupt to the completion of interrupt
processing.
Internal bus
IL Interupt level setting bit of interupt control register (ICR)
PS Processor status
I Interrupt enable flag
ILM Interrupt level mask register
IR Instruction register
FF Flip flop
1. The peripheral generates an interrupt request.
2. When the interrupt enable bit in the peripheral is set to enabled, the peripheral generates an interrupt
request to the interrupt controller.
3. The interrupt controller that received the interrupt request determines the priority of interrupts
simultaneously requested and posts the interrupt level (IL) corresponding to the appropriate interrupt
request to the CPU.
4. The CPU compares the interrupt level (IL) requested from the interrupt controller with the value of the
interrupt level mask register (ILM).
5. If the interrupt request is preferred to the interrupt mask register (ILM), the interrupt enable flag (CCR:
I) is checked.
6. When an interrupt is enabled by the interrupt enable flag (CCR: I = 1), the requested interrupt level (IL)
is set to the interrupt level mask register (ILM) after completion of the current instruction execution.
7. The values of the dedicated registers are saved, and processing transfers to interrupt processing.
8. The program clears the interrupt request generated from the peripheral and executes the interrupt return
instruction (RETI) to terminate interrupt processing.
Figure 3.5-6 Operation of Hardware Interrupt
PS,PC
7
Micro code
F MC-16LXCPU
2
Other peripheral function
Peripheral function of
interrupt request generate
Enable FF
AND
Factor FF
8
1
RAM
PS I ILM
IR
Check
Comparator
6
5
Level
comparator
2
Interrupt controller
CHAPTER 3 CPU
4
3
Interrupt
level IL
73