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CHAPTER 9 Watch timer
9.5
Explanation of Operation of Watch Timer
The watch timer operates as an interval timer or an oscillation stabilization wait time
timer of the sub clock.It also supplies an operation clock to the watchdog timer.
I Watch timer counter
The watch timer counter continues incrementing in synchronization with the sub clock (SCLK) while the
sub clock (SCLK) is operating.
G
Clearing watch timer counter
The watch timer counter is cleared to "0000
• Power on reset
• The mode transits to the stop mode.
• The watch timer clear bit (WTR) in the watch timer control register (WTC) is set to 0.
Note:
When the watch timer counter is cleared, the interrupts of the watchdog timer and interval
timer that use the output of the watch timer counter are affected.
Before clearing the watch timer by setting the watch timer clear bit (WTR) in the watch timer
control register (WTC), set the overflow interrupt enable bit (WTIE) in the WTC register to
disable the watch timer for interrupts.Before enabling interrupts, set the WTC overflow flag
bit (WTOF) to clear the interrupt request.
I Interval Timer Function
The watch timer can be used as an interval timer by generating an interrupt at each interval time.
G
Settings when using watch timer as interval timer
Operating the watch timer as an interval timer requires the settings shown in Figure 9.5-1.
: Used bit
: Unused bit
• When the value set by the interval time select bits (WTC1, WTC0) in the watch timer control register
(WTC) is reached, the overflow flag bit in the WTC register is set to 1 (WTC: WTOF = 1).
• When the overflow flag bit is set (WTC: WTOF = 1) with the overflow interrupt of the watch timer
counter enabled (WTC: WTIE = 1), an interrupt request is generated.
286
Figure 9.5-1 Setting of Watch Timer
bit7
6
5
WTC
WDCS
SCE WTIE
WTOF WTR
" when:
H
4
3
2
1
bit0
WTC2
WTC1
WTC0
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