Fujitsu MB90895 Series Hardware Manual page 422

CHAPTER 14 UART0
G
Timing of transmit interrupt request
A transmission interrupt request is generated when the transmit data write flag bit (SSR0: TDRE) is set
with transmission interrupts enabled (SSR0: TIE = 1).
Note: If the transmission in progress is disabled (SCR0: TXE = 1, and reception is also disabled
with RXE = 0 in operation mode 1), the transmit data write flag bit is set (SSR0: TDRF = 1),
the transmission shift register stops shifting, then the UART0 is disabled. That transmit data
is transmitted which is already written to serial output data register 0 (SODR0) before
transmission stops (SODR).
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