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Table 13.3-2 Function of Each Bit of A/D Control Status Register (High) (ADCS: H) (1/2)
bit name
bit8
Reserved: reserved bit
bit9
STRT:
A/D conversion software
start bit
bit10
STS1, STS0:
bit11
A/D conversion start
trigger select bits
bit12
PAUS:
Pause flag bit
bit13
INTE:
Interrupt request flag bit
bit14
INT:
Interrupt request flag bit
Always set this bit to "0".
This bits starts the 8-/10-bit A/D converter by software.
When set to "1": Starts 8-/10-bit A/D converter
•
If A/D conversion pauses in the pause-conversion mode, it is
resumed by writing "1" to the STRT bit.
When set to "0": Disabled.The state remains unchanged.
Read: The bit returns "1" when byte/word instructions.
The bit returns "0" when read-modify-write instructions.
Note:
Do not perform forcible termination (BUSY = 0) and software
start (STRT = 1) of the 8-/10-bit A/D converter simultaneously.
These bits select the trigger to start the 8-/10-bit A/D converter.
If two or more start triggers are set (except STS1, STS0="00
8-/10-bit A/D converter is started by the first-generated start trigger.
Note:
Start trigger setting should be changed when the operation of
resource generating a start trigger is stopped.
This bit indicates the A/D conversion operating state when the
2
EI
OS function is used.
•
The PAUS bit is enabled only when the EI
•
A/D conversion pauses while the A/D conversion results are
transferred from the A/D data register (ADCR) to
memory.When A/D conversion pauses, the PAUS bit is set to
"1".
•
After transfer of the A/D conversion results to memory, the 8-/
10-bit A/D converter automatically resumes A/D
conversion.When A/D conversion is started, the PAUS bit is
cleared to "0".
This bit enables or disables output of an interrupt request.
•
When the interrupt request flag bit is set with an interrupt
request enabled (INTE = 1), an interrupt request is generated.
Note:
Always set this bit to 1 when the EI
This bit indicates that an interrupt request is generated.
•
When A/D conversion is terminated and its results are stored in
the A/D data register (ADCR), the INT bit is set to "1".
•
When the interrupt request flag bit is set (INT = 1) with an
interrupt request enabled (INTE = 1), an interrupt request is
generated.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
2
When EI
OS function started: Cleared
Note:
To clear the INT bit, write "0" when the 8-/10-bit A/D converter
is stopped.
CHAPTER 13 8/10-bit A/D converter
Function
2
OS function is used.
2
OS function is used.
"), the
B
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