Interrupt Of Uart1 - Fujitsu MB90895 Series Hardware Manual

CHAPTER 15 UART1
15.4

Interrupt of UART1

The UART1 has a receive and a transmit interrupts, and the following factors can issue
interrupt requests.
• Receive data is loaded to the serial input data register 1 (SIDR1).
• A receive error (parity error, overrun error, framing error) occurs.
• When send data transferred from the output data register 1 (SODR1) to transmit shift
register
Also, each of these interrupt factors supports the expansion intelligent I/O service
2
(EI OS).
I Interrupt of UART1
The UART1 interrupt control bits and interrupt factors are shown in .
Table 15.4-1 UART1 Interrupt Control Bit and Interrupt Factor
Trans-
missio
n/
Recep
tion
Recepti
on
Transm
ission
: Used bit
: Unused bit
448
Operating
Interrupt mode
request
flag bit
0 1 2
SSR1:
RDRF
SSR1:
ORE
SSR1:
FRE
SSR1:PE
SSR1:
TDRE
Interrupt
Interrupt Factor factor enable
Receive data loaded
into serial input data
register 1 (SIDR1)
Overrun error
SSR1: RIE
Framing error
generating parity
error
Transfer of transmit
data completed
from serial output SSR1: TIE
data register
(SODR1)
Clear of the
Interrupt-
bit request Flag
Reading receive
data
Writing 0 to
receive error flag
clear bit (SCR1
register bit 10:
REC)
Writing transmit
data