Generation Of Receive Interrupt And Timing Of Flag Set; Fig. 12.9 Reception And Timing Of Flag Set - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

12.5.1 Generation of Receive Interrupt and Timing of Flag Set

Interrupts atreceiving include the receive completion (SSR0/1: RDRF), and the receive error (SSR0/1: PE,
ORE, FRE).
n Generation of receive interrupt and timing of flag set
At reception, the receive data is stored in the input data register (SIDR0/1) when the stop bit is detected
(operation mode is 0 or 1) or when the end bit of the data (D7) is detected (operation mode is 2). When a
receive error is already occurred at this point, the error flag (SSR0/1: PE, ORE, FRE) is set and then the
receive data full flag (SSR0/1: RDRF) is set to 1. In each operation mode, the value of SIDR0/1 is invalid
data when any one of the error flags is 1.
• Operation mode 0 (asynchronous, normal mode)
When RDRF is set to 1 at detection of the stop bit, and a receive error is already occurred at this point, the
error flag (PE, ORE, FRE) is set.
• Operation mode 1 (asynchronous, multiprocessor mode)
When RDRF is set to 1 at detection of the stop bit, and a receive error is already occurred at this point, the
error flag (ORE, FRE) is set. No parity error can be detected.
• Operation mode 2 (synchronous, normal mode)
When RDRF is set to 1 at detection of the end bit (D7) of receive data, and a receive error is already
occurred at this point, the error flag (ORE) is set. Neither parity nor framing error can be detected. Figure
12.9 shows the reception and the timing of the flag set.
Receive data
(operation mode 0)
Receive data
(operation mode 1)
Receive data
(operation mode 2)
PE, ORE, FRE*
RDRF
* : The PE flag cannot be used in mode 1.
The PE and FRE flags cannot be used in mode 2.
ST : Start bit
SP : Stop bit
A/D : Address/data select bit for mode 2 (multiprocessor mode)
• Timing of receive interrupt generation
Immediately after any one of the RDRF, PE, ORE, and FRE flags is set to 1 when the receive interrupt is
enabled (SSR0/1: RIE = 1), a receive interrupt request (#37, #39) is issued.
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
ST D0 D1
ST D0 D1
D0 D1

Fig. 12.9 Reception and Timing of Flag Set

12-20
D5 D6 D7/P SP
D6 D7 A/D SP
D4 D5 D6 D7
Generation of
receive interrupt