Fujitsu MB90895 Series Hardware Manual page 648

APPENDIX
G
Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of general-
purpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
Figure A.4-6 Example of register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7
G
Program counter relative branch addressing (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the program
counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is
not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte
bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to
23 are indicated by the program bank register (PCB).
Figure A.4-7 Example of program counter relative branch addressing (rel)
BRA 10H
630
(This instruction reads data by register indirect addressing with a
base index and stores it in A.)
Before execution
A
RW1
RW7
After execution
A
RW1
RW7
(This instruction causes an unconditional relative branch.)
Before execution
PC 3 C 2 0
After execution
PC 3 C 3 2
0 7 1 6 2 5 3 4
D 3 0 F DTB 7 8 78D411H
+
78D410H
0 1 0 1
2 5 3 4 F F E E
D 3 0 F DTB 7 8
0 1 0 1
PCB 4 F
4F3C32H
4F3C21H
PCB 4 F
4F3C20H
Memory space
F F
E E
Memory space
Next instruction
1 0
6 0
BRA 10H