Fujitsu MB90895 Series Hardware Manual page 231

Table 6.3-1 Functions of the Watching Timer Control Register (WDTC)
bit name
bit0 WT1, WT0:
bit1 Interval time select bits
bit2 WTE:
Watchdog timer control
bit
bit6 Unused bits
bit3 PONR, WRST, ERST,
to SRST:
bit7 Reset Factor Bit
Function
These bits set the interval time of the watchdog timer.
'The time interval when the watch timer is used as the clock
source to the watchdog timer (watchdog clock select bit WDCS
= 0) is different from when the main clock mode or the PLL
clock mode is selected as the clock mode and the WDCS bit in
the watch timer control register (WTC) is set to "1" as shown in
Figure 6.3-2 according to the settings of the WTC register.
• Settings of the WTC register.
• Write data after the watchdog timer is started is ignored.
• These are write-only bits.
This bit starts or clears the watchdog timer.
When set to "0" (first time after reset): The watchdog timer
is started.
When set to "0" (second or subsequent): The watchdog
timer is cleared.
Read: The value is undefined.
Write: No effect
These bits indicate reset factors.
• When a reset occurs, the bit corresponding to the reset factor
is set to "1".After a reset, the reset factor can be checked by
reading the watchdog timer control register (WDTC).
• These bits are cleared after the watchdog timer control
register (WDTC) is read.
Note:
No bit value other than the PONR bit after power-on reset is
assured.If the PONR bit is set at read, other bit values should
be ignored.
CHAPTER 6 Watchdog timer
213