Fujitsu MB90895 Series Hardware Manual page 135

Table 3.7-3 PLL multipliler setting in PSCCR:CS2 and CKSCR:CS1/CS0
CS2
0
0
0
0
1
1
1
1
Note: This feature is not provided for the MB90V495G.This register therefore returns "1"
whenever read.
CS1 CS0
×
0 0
1 HCLK (4 MHz)
×
0 1
2 HCLK (8 MHz)
×
1 0
3 HCLK (12 MHz)
×
1 1
4 HCLK (16 MHz)
×
0 0
2 HCLK(8 MHz)
×
0 1
4 HCLK(16 MHz)
1 0 Unavailable
1 1 Unavailable
(Calculated assuming a frequency of 4 MHz)
Function
CHAPTER 3 CPU
117