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I List of Registers and Reset Values of 8-/10-bit A/D Converter
Figure 13.3-1 List of Registers and Reset Values of 8-/10-bit A/D Converter
A/D control status register upper
A/D control status register lower
A/D data register upper (ADCR: H)
A/D data register lower (ADCR: L)
Analog input enable register (ADER)
: Undefined
I Generation of Interrupt from 8-/10-bit A/D Converter
In the 8-/10-bit A/D converter, when the A/D conversion results are stored in the A/D data register
(ADCR), the interrupt request flag bit in the A/D control status register (ADCS: INT) is set to "1".When an
interrupt request is enabled (ADCS: INTE = 1), an interrupt is generated.
bit
(ADCS: H)
bit
(ADCS: L)
bit
bit
bit
CHAPTER 13 8/10-bit A/D converter
15
14
13
12
11
0
0
0
0
0
7
6
5
4
3
0
0
0
0
0
15
14
13
12
11
0
0
1
0
1
7
6
5
4
3
7
6
5
4
3
1
1
1
1
1
10
9
8
0
0
0
2
1
0
0
0
0
10
9
8
2
1
0
2
1
0
1
1
1
355
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