Fujitsu MB90895 Series Hardware Manual page 305

• The overflow flag bit (WTC: WTOF) is set when the interval time is reached at the starting point of the
timing at which the watch timer is finally cleared.
G
Clearing overflow flag bit (WTC: WTOF)
When the mode is switched to the stop mode, the watch timer is used as an oscillation stabilization wait
time timer of sub clock. The WTOF bit is cleared concurrently with mode switching.
I Setting Operation Clock of Watchdog Timer
The watchdog clock select bit (WDCS) in the watch timer control register (WTC) can be used to set the
clock input source of the watchdog timer.
When using the sub clock as the machine clock, always set the WDCS bit to "0" and select the output of the
watch timer.
I Oscillation Stabilization Wait Time Timer of Sub clock
When the watch timer returns from the power-on reset and the stop mode, it functions as an oscillation
stabilization wait time timer of sub clock.
• The sub clock oscillation stabilization wait time is fixed at 2
CHAPTER 9 Watch timer
14
/SCLK (SCLK: sub clock frequency).
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