Fujitsu MB90895 Series Hardware Manual page 336

CHAPTER 10 8/16-bit PPG timer
G
Output waveform in 8-bit PPG output 2-channel independent operation mode
• The High and Low pulse widths to be output are determined by adding 1 to the value in the PPG reload
register and multiplying it by the count clock cycle.
The equations for calculating the pulse width are shown below:
PL=T × (L
PH=T × (H
PL: Low width of output pulse of PPG1 pin
PH: High width of output pulse of PPG1 pin
L : Values of 8 bits in PPG reload register (PRLL0)
0
H : Values of 8 bits in PPG reload register (PRLH0)
0
L : Values of 8 bits in PPG reload register (PRLL1)
1
H : Values of 8 bits in PPG reload register (PRLH1)
1
T: Count clock cycle
Figure 10.5-7 shows the output waveform in the 8+8-bit PPG output operation mode.
Figure 10.5-7 Output Waveform in 8+8-bit PPG Output Operation Mode
PPG operating enable bit
(PEN0, PEN1)
PPG0 output pin
PPG1 output pin
L : 8-bit value of PPG reload register (PRLL0)
0
H : 8-bit value of PPG reload register (PRLH0)
0
H : 8-bit value of PPG reload register (PRLL1)
1
L : 8-bit value of PPG reload register (PRLH1)
1
T : Count clock cycle
318
+1) × (L
+1)
0 1
+1) × (H
+1)
0 1
Operating start
T × (L
+1)
0
T × (L +1) × (L
0
T × (H
+1)
0
T × (H
+1)
1
Operating stop
+1) × (H
+1)
0 1