Fujitsu MB90895 Series Hardware Manual page 333

G
Output waveform in 16-bit PPG output operation mode
• The High and Low pulse widths to be output are determined by adding 1 to the value in the PPG reload
register and multiplying it by the count clock cycle.For example, if the value in the PPG reload register
is "0000 ", the pulse width has one count clock cycle, and if the value is "FFFF
H
65,536 count clock cycles.
The equations for calculating the pulse width are shown below:
PL=T × (L+1)
PH=T × (H+1)
PL: Low width of output pulse
PH: High width of output pulse
L: Values of 16 bits in PPG reload register (PRLL0 + PRLL1)
H: Values of 16 bits in PPG reload register (PRLH0 + PRLH1)
T: Count clock cycle
Figure 10.5-5 shows the output waveform in the 8+8-bit PPG output operation mode.
Figure 10.5-5 Output waveform in 16-bit PPG output operation mode
PPG operating enable bit
(PEN)
PPG output pin
L : 16-bit value of PPG reload register (PRLL1+PRLL0)
H : 16-bit value of PPG reload register (PRLH1+PRLH0)
T : Count clock cycle
Operating start
T × (L+1) T × (H+1)
CHAPTER 10 8/16-bit PPG timer
", the pulse width has
H
Operating stop
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