Fujitsu MB90895 Series Hardware Manual page 432

16 bit, controller manual
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CHAPTER 14 UART0
G
Inter-CPU connection method
Either 1-to-1 connection or master/slave type connection can be selected for the inter-CPU controller.In
both cases, the data length, parity, synchronous or asynchronous mode, etc., must be the same for all
CPUs.The operation modes are selected as follows.
• For one-to-one connection, the same operation mode (either operation mode 0 or 2) must be adopted for
the two CPUs.For asynchronous transfer, set operation mode 0 (SMR0: MD1, MD0 = "00
clock-synchronous transfer, set operation mode 2 (SMR0: MD1, MD0 = "10
• For master/slave connection, set operation mode 1 (SMR0: MD1, MD0 = "01
1 is set, use the device as the master.For this connection, select no parity and a data length of 8 bits.
G
Synchronous type
For the operation modes, either the asynchronous mode (start-stop synchronization) or the clock-
synchronous mode can be selected.
G
Signal type
The UART0 can only handle the NRZ (Non Return to Zero) data format.
G
Start of transmission/reception
• Transmission starts when the transmission enable bit (SCR0: TXE) in the serial control register is set to
"1".
• Reception starts when the reception enable bit of the serial control register (SCR0: RXE) is set to "1".
G
Stop of transmission/reception
• Transmission starts when the transmission enable bit (SCR0: TXE) in the serial control register is set to
"0".
• Reception starts when the reception enable bit (SCR0: RXE) in the serial control register is set to "0".
G
Stop during transmission/reception
• When the reception in process is disabled (SCR0: RXE = 0) (during data input to the reception shift
register), the device stops reception after receiving the current frame of data completely and storing the
received data to serial input data register 0 (SIDR0).
• When transmission is disabled during transmission (during data output from the transmission shift
register) (SCR1 register bit 8: TXE = 0), transmission stops after transmission of one frame to the
transmission shift register from the serial output data register 1
414
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B
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B
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B

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