Fujitsu MB90895 Series Hardware Manual page 272

CHAPTER 8 16-bit reload timer
I Generation of Interrupt Request from 16-bit Reload Timer
When the 16-bit reload timer is started and the count value of the 16-bit timer register is decremented from
"0000 " to "FFFF
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register is set to "1" (TMCSR: UF). If an underflow interrupt is enabled (TMCSR: INTE = 1), an interrupt
request is generated.
254
", an underflow occurs.When an underflow occurs, the UF bit in the timer control status
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