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CHAPTER 7 16-bit I/O timer
I Generation of Interrupt Request from 16-bit Input/Output Timer
The 16-bit input/output timer can generate an interrupt request as a result of the following factors:
G
Overflow in 16-bit free-run timer
In the 16-bit input/output timer, when the 16-bit free-run timer overflows, the overflow generation flag bit
in the timer counter control status register (TCCS: IVF) is set to "1".When an overflow interrupt is enabled
(TCCS: IVFE = 1), an interrupt request is generated.
G
Edge detection by capture function
The counter value of the 16-bit free-run timer actually read when the edge of the external signal input to the
input pins (IN0 to IN3) is detected is stored in the input capture data registers (IPC0 to IPC3)
corresponding to the input pins (IN0 to IN3). When the input capture interrupt corresponding to the channel
generating an interrupt request is enabled (ICS: ICE), an interrupt request is generated.
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