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16.3.17
Receive complete interrupt enable register (RIER)
The reception complete interrupt enable register (RIER) enables or disables a reception
complete interrupt for each message buffer.
I Receive complete interrupt enable register (RIER)
Figure 16.3-25 Receive complete interrupt enable register (RIER)
7
6
5
R/W
R/W
R/W
R/W
: Read/Write
: Reset value
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
bit0
RIE0
bit1
RIE1
bit2
RIE2
bit3
RIE3
bit4
RIE4
bit5
RIE5
bit6
RIE6
bit7
RIE7
Reset value
0 0 0 0 0 0 0 0
B
Reception interrupt enable bit 0 (Message buffer 0)
Disable reception compiete interrupt
0
1
Enables reception complete interrupt
Reception interrupt enable bit 1 (Message buffer 1)
Disable reception complete interrupt
0
1
Enables reception complete interrupt
Reception interrupt enable bit 2 (Message buffer 2)
Disable reception complete interrupt
0
1
Enables reception complete interrupt
Reception interrupt enable bit 3 (Message buffer 3)
Disable reception complete interrupt
0
1
Enables reception complete interrupt
Reception interrupt enable bit 4 (Message buffer 4)
Disable reception complete interrupt
0
1
Enables reception complete interrupt
Reception interrupt enable bit 5 (Message buffer 5)
Disable reception complete interrupt
0
1
Enables reception complete interrupt
Reception interrupt enable bit 6 (Message buffer 6)
Disable reception complete interrupt
0
1
Enables reception complete interrupt
Reception interrupt enable bit 7 (Message buffer 7)
Disable reception complete interrupt
0
1
Enables reception complete interrupt
CHAPTER 16 CAN controller
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