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CHAPTER 15 UART1
15.4.1
Generation of Receive Interrupt and Timing of Flag Set
Interrupts at receiving include the receive completion (SSR1 register bit 12: RDRF), and
the receive error (SSR1 register bit 15, 14, 13: PE, ORE, FRE).
I Generation of Receive Interrupt and Timing of Flag Set
G
Receive data load flag and each receive error flag sets
When data is received, it is stored in the serial input data register (SIDR) when the stop bit is detected (in
operation modes 0 and 1: Asynchronous normal mode, Asynchronous multiprocessor mode) or when the
last bit of receive data (SIDR1 register bit 7: D7) is detected (in operation mode 2: Clock synchronous
normal mode). When a receive error occurs, the error flags (SSR1 register bit 15, 14, 13: PE, ORE, FRE)
and receive data load flag (SSR1 register bit 12: RDRF) are set. When a reception error occurs, the
corresponding error flag (bit 15, 14, 13 of SSR1 register: PE, ORE, or FRE) is set and the receive data load
flag (bit 12 of SSR1 register: RDRF) is set as well. In each operation mode, the received data in the serial
input data register 0 (SIDR1) is invalid if either error flag is set. If any of the flags is set to the each
operation mode, the serial input data registers 1 (SIDR1) that have received are invalid.
Operation mode 0 (Asynchronous normal mode)
The receive data load flag bit (SSR1 register bit 12: RDRF) is set when the stop bit is detected.The error
flags (SSR1 register bit 15, 14, 13: PE, ORE, FRE) are set when a receive error occurs.
Operation mode 1 (Asynchronous multiprocessor mode)
The receive data load flag bit (SSR1 register bit 12: RDRF) is set to 1 when the stop bit is detected.The
error flags (SSR1 register bit 14, 13: ORE, FRE) are set when a receive error occurs.A parity error (SSR1
register bit 15: PE) cannot be detected.
Operation mode 2 (Clock synchronous mode)
The receive data load flag bit (SSR1 register bit 12: RDRF) is set to "1" when the last bit of receive data
(SIDR1 register bit 7: D7) is detected.The error flags (SSR1 register bit 14: ORE) are set when a receive
error occurs.A parity error (SSR1 register bit 15: PE) and framing error (SSR1 register bit 13: FRE) cannot
be detected.
Reception and timing of flag set are shown in .
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