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CHAPTER 3 CPU
3.2.4.3
Interrupt Level Mask Register (PS: ILM)
The interrupt level mask register (ILM) is a 3-bit register indicating the interrupt level
accepted by the CPU.
I Interrupt level mask register (ILM)
Figure 3.2-14 shows the configuration of the interrupt level mask register (ILM).
Figure 3.2-14 Configuration of Interrupt Level Mask Register (ILM)
bit15
PS
ILM2
The interrupt level mask register (ILM) indicates the level of an interrupt that the CPU is accepting for
comparison with the values of the interrupt level setting bits (ICR: IL2 to IL0) set according to interrupt
requests from each resource. The CPU performs interrupt processing only when an interrupt with a lower
value (interrupt level) than that indicated by the interrupt level mask register (ILM) is requested with an
interrupt enabled (CCR: I = 1).
• When an interrupt is accepted, its interrupt level value is set in the interrupt level mask register (ILM).
Thereafter, an interrupt with a level value lower than the set level value is not accepted.
• At a reset, the interrupt level mask register (ILM) is always set to 0 to enter the interrupt-disabled
(highest interrupt level) state.
• The assembler instruction can use the 8-bit immediate value transfer instruction that is transferred to the
interrupt level mask register (ILM), but only the lower 3 bits of that data is actually used.
Table 3.2-3 Interrupt Level Mask Register (ILM) and Interrupt Level (High/Low)
ILM2
0
0
0
0
1
1
1
1
Note:
For details of interrupt, see 1.5 Interrupt.
44
RP
ILM
14
13 12 11 10
9
B4 B3 B2 B1 B0
ILM1 ILM0
ILM1
0
0
1
1
0
0
1
1
CCR
8
7
6
5
4
3
I
S
T
N
-
ILM0
Interrupt
Level
0
0
1
1
0
2
1
3
0
4
1
5
0
6
1
7
2
1
bit0
ILM reset value
Z
V
C
000
B
Interrupt Level (High/Low)
high (interrupt prohibited)
↑
↓
low
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