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CHAPTER 15 UART1
I List of Registers in UART1
Serial control register 1 (SCR1)
Serial mode register 1 (SMR1)
Serial status register 1 (SSR1)
Serial input data register 1 (SIDR1)
/serial output data register 1 (SODR1)
Note : Function as SIDR1 when reading, function as SODR1 when writing.
Communication prescaler control
register 1 (CDCR1)
: Undefined
I Interrupt Request Generation by UART1
G
Reception Interrupt
• When receive data is loaded to the serial input data register (SIDR1), the receive data load flag bit (bit
12: RDRF) in the serial status register (SSR1) is set to "1".When a receive interrupt is enabled (bit 9:
RIE = 1), a receive interrupt request is generated to the interrupt controller.
• When either a framing error, overrun error, or parity error occurs, the framing error flag bit (bit 13:
FRE), the overrun error flag bit (bit 14: ORE), or parity error flag bit (bit 15: PE) in the serial status
register (SSR1) are set to 1 according to the error occurred. When a receive interrupt is enabled (bit 9:
RIE = 1), a receive interrupt request is generated to the interrupt controller.
G
Transmission Interrupt
When transmit data is transferred from the serial output data register (SODR1) to the transmit shift register,
the transmit data empty flag bit (bit 11: TDRE) in the serial status register (SSR1) is set to "1".If a transmit
interrupt is enabled (bit 8: TIE = 1), a transmit interrupt is requested.
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Figure 15.3-1 List of Registers and Reset Values in UART1
bit
15
14
13
12
0
0
0
0
bit
7
6
5
0
0
0
0
bit
15
14
13
12
0
0
0
0
bit
7
6
5
bit
15
14
13
12
0
11
10
9
8
0
1
0
0
4
3
2
1
0
0
0
0
0
11
10
9
8
1
0
0
0
4
3
2
1
0
11
10
9
8
0
0
0
0
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