Fujitsu MB90895 Series Hardware Manual page 330

CHAPTER 10 8/16-bit PPG timer
• When an underflow occurs, the underflow generation flag bit in the channel that causes an underflow is
set (PPGC0: PUF0 = 1, PPGC1: PUF1 = 1).If an interrupt request is enabled at the channel that causes
an underflow (PPGC0: PIE0 = 1, PPGC1: PIE1 = 1), the interrupt request is generated.
G
Output waveform in 8-bit PPG output 2-channel independent operation mode
• The High and Low pulse widths to be output are determined by adding 1 to the value in the PPG reload
register and multiplying it by the count clock cycle.For example, if the value in the PPG reload register
is 00 H, the pulse width has one count clock cycle, and if the value is FF H, the pulse width has 256
count clock cycles.
The equations for calculating the pulse width are shown below:
=T × (L+1)
P
L
=T × (H+1)
P
H
P : Low width of output pulse
L
P : High width of output pulse
H
L: Values of 8 bits in PPG reload register (PRLL0 or PRLL1)
H: Values of 8 bits in PPG reload register (PRLH0 or PRLH1)
T: Count clock cycle
Figure 10.5-3 shows the output waveform in the 8-bit PPG output 2-channel independent operation mode.
Figure 10.5-3 Output waveform in 8-bit PPG output 2-channel independent operation mode
PPG operating enable bit
(PEN)
PPG output pin
L : Value of PPG reload register (PRLL)
H : Value of PPG reload register (PRLH)
T : Count clock cycle
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Operating start
T × (L+1) T × (H+1)
Operating stop