Fujitsu MB90895 Series Hardware Manual page 565

I Procedure for Receiving Message Buffer (x)
Figure 16.5-5 shows the procedure for the receiving setting.
Setting of bit timing
Setting of frame for mat
Setting of ID
Setting of acceptance filter
Processing message stored
(processing receiving completed interrupt)
G
Procedure for Receiving Message Buffer (x)
After presetting, perform the following setting:
G
Setting reception complete interrupt
• To generate a reception complete interrupt, set the RIEx bit in the reception complete interrupt enable
register (RIER) to "1".
• To disable a reception complete interrupt (RCR: RCx = 1), set the RIEx bit to "0".
Figure 16.5-5 Flowchart of Procedure for Receive Setting
Using Message Buffre select
Message buffer validating register (BVALR)
Setting reception complete interrupt
Receive complete interrupt enable register (RIER)
Canceling bus halt HALT=1
If received message
Receive bytes count read
Received message is read
Reception complete bits cleared
START
Bit timing register (BTR)
IDE register (IDER)
ID register (IDR)
Acceptance mask select register (AMSR)
Acceptance mask registers (AMR0,1)
N
RCx=1 ?
Y
N
Receive overrun?
ROVRx=0 ?
Y
RCx=0
END
CHAPTER 16 CAN controller
Reception overrun bits cleared
ROVRx=0
547