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G
Operation at reset
• When the CPU is reset, the value of the DDR5 is initialized to "0".Consequently, all output buffers are
set to "OFF" (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR5 is not initialized by reset. Therefore, when using port 5 as an output port, it is necessary to set
output data in the PDR5, and then set the bit in the DDR5 corresponding to the output pin to "1" and to
output.
G
Operation in stop mode, timebase timer mode or watch mode
• When the pin state specification bit of the low power consumption mode control register (LPMCR:
SPL) is "1", at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the
high- impedance state. The output buffer is set forcibly to "OFF" irrespective of the value of the DDR5.
Table 4.7-4 shows the state of the port 5 pins.
Table 4.7-4 The state of the port 5 pins
Pin Name
P50/AN0,
P57/AN7
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
Normal
Sleep
Operation
mode
General-
General-
purpose I/O
purpose I/O
ports
ports
Stop Mode,
Timebase Timer Mode or Watch Mode]
SPL=0
General-purpose I/O
Input cut off, and output
ports
becomes Hi-Z
CHAPTER 4 I/O PORT
SPL=1
189
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